1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly to a gallium nitride-on-silicon interface that uses multiple buffer layers of aluminum compounds, and an associated fabrication process.
2. Description of the Related Art
Gallium nitride (GaN) is a Group III/Group V compound semiconductor material with wide bandgap (3.4 eV), which has optoelectronic, as well as other applications. Like other Group III nitrides, GaN has a low sensitivity to ionizing radiation, and so, is useful in solar cells. GaN is also useful in the fabrication of blue light-emitting diodes (LEDs) and lasers. Unlike previous indirect bandgap devices (e.g., silicon carbide), GaN LEDs are bright enough for daylight applications. GaN devices also have application in high power and high frequency devices, such as power amplifiers.
GaN LEDs and GaN-based devices are conventionally fabricated using a metalorganic chemical vapor deposition (MOCVD) for deposition on a sapphire substrate. Zinc oxide and silicon carbide (SiC) substrate are also used due to their relatively small lattice constant mismatch. However, these substrates are expensive to make, and their small size also drives fabrication costs. For example, the state-of-the-art sapphire wafer size is relatively small when compared to silicon wafers. The low thermal and electrical conductivity constraints associated with sapphire make device fabrication more difficult. For example, all contacts must be made from the top side. This contact configuration complicates contact and package schemes, resulting in a spreading-resistance penalty and increased operating voltages. The poor thermal conductivity of sapphire [0.349 (W/cm-° C.)], as compared with that of Si [1.49 (W/cm-° C.)] or SiC, also prevents efficient dissipation of heat generated by high-current devices, such as laser diodes and high-power transistors, consequently inhibiting device performance.
To minimize costs, it would be desirable to integrate GaN device fabrication into more conventional Si-based IC processes, which has the added cost benefit of using large-sized (Si) wafers. Si substrates are of particular interest because they are less expansive and they permit the integration of GaN-based photonics with well-established Si-based electronics. The cost of a GaN heterojunction field-effect transistor (HFET) for high frequency and high power application could be reduced significantly by replacing the expensive SiC substrates that are conventionally used.
FIG. 1 is a graph depicting the lattice constants of GaN, Si, SiC, AlN and sapphire (prior art). There are two fundamental problems associated with GaN-on-Si device technology. First, there is a lattice mismatch between Si and GaN. The difference in lattice constants between GaN and Si, as shown in the figure, results in a high density of defects from the generation of threading dislocations. This problem is addressed by using a buffer layer of AlN, InGaN, AlGaN, or the like, prior to the growth of GaN. The buffer layer provides a transition region between the GaN and Si.
FIG. 2 is a graph depicting the thermal expansion coefficients (TECs) of GaN, Si, SiC, AlN, and sapphire (prior art). An additional and more serious problem exists with the use of Si, as there is also a thermal mismatch between Si and GaN. GaN-on-sapphire experiences a compressive stress upon cooling. Therefore, film cracking is not as serious of an issue as GaN-on-Si, which is under tensile stress upon cooling, causing the film to crack when the film is cooled down from the high deposition temperature. The thermal expansion coefficient mismatch between GaN and Si is about 54%.
The film cracking problem has been analyzed in depth by various groups, and several methods have been tested and achieve different degrees of success. The methods used to grow crack-free layers can be divided into two groups. The first method uses a modified buffer layer scheme. The second method uses an in-situ silicon nitride masking step. The modified buffer layer schemes include the use of a grading AlGaN buffer layer, AlN interlayers, and AlN/GaN or AlGaN/GaN-based superlattices.
Although the lattice buffer layer may absorb part of the thermal mismatch, the necessity of using temperatures higher than 1000° C. during epi GaN growth and other device fabrication processes may cause wafer deformation. The wafer deformation can be reduced with a very slow rate of heating and cooling during wafer processing, but this adds additional cost to the process, and doesn't completely solve the thermal stress and wafer deformation issues.
It is generally understood that a buffer layer may reduce the magnitude of the tensile growth stress and, therefore, the total accumulated stress. However, from FIG. 2 it can be seen that there is still a significant difference in the TEC of these materials, as compared with GaN. Therefore, thermal stress remains a major contributor to the final film stress.
D. Zubia et al. describe an approach to the heteroepitaxy of lattice mismatched semiconductors, which is called nanoheteroepitaxy. The theory developed in their research shows that the 3D stress relief mechanisms that are active when an epilayer is nucleated as an array of nanoscale islands on a compliant patterned substrate significantly reduces the strain energy in the epilayer and extends the critical thickness of a film dramatically.
It would be advantageous if the thermal mismatch problem associated with GaN-on-Si device technology could be practically eliminated by using aluminum compound buffer layers as a thermal interface interposed between the GaN and Si layers.
It would be advantageous if the aluminum compound buffer layer approach to a GaN-on-Si interface could be augmented with the use of nanoscale lateral epitaxial overgrowth (NLEO) GaN, to further reduce the defect density.